/* SPDX-License-Identifier: GPL-2.0 */
/*
 * pmc_operate.h - pmc csp head file
 *
 * Copyright (C) 2016-2018, LomboTech Co.Ltd.
 * Author: lomboswer <lomboswer@lombotech.com>
 *
 */

#include <linux/io.h>
#include <mach/csp.h>

#define IRQ_FLAGS		IRQF_NO_SUSPEND

#define PM_CLK_CTRL		(0x0020)
#define PMC_LD_EN		(0x0024)
#define PMC_LD_INT_EN		(0x0028)
#define PMC_LD_INT_CLR		(0x002C)
#define PMC_LD_PEND		(0x0030)
#define LFEOSC_FANOUT_CFG	(0x006c)
#define PM_PE			(0x0460)
#define PM_FB_EN		(0x0464)
#define PM_INT_EN		(0x0468)
#define PM_PEND_CLR		(0x046C)
#define PM_PEND			(0x0470)
#define PM_PE1			(0x0474)
#define PM_PKT			(0x0484)
#define PM_WKAE0_CTRL		(0x0480)
#define PM_PWR_KRY_CTRL		(0x0488)

#define PM_WAKEX_SAMP_CTRL	(0x0500)
#define PM_WAKE1_FB_CTRL	(0x0504)
#define PM_WAKE2_FB_CTRL	(0x0510)

#define LOCK_CTRL		(0x0700)
#define SYS_STAT		(0x0728)
#define LOCK_CTRL_KEY_FIELD	(0x0EA5)

#define PWR_PE1_PUP		BIT(24)
#define PWR_PE1_REN		BIT(23)
#define PWR_PE0_PUP		BIT(21)
#define PWR_PE0_REN		BIT(20)
#define SYS_RESETN_IRQ		BIT(18)
#define ALARM_INT_IRQ		BIT(17)
#define GPADC_DET_IRQ		BIT(16)
#define PWR_KEY_RELEASE_IRQ	BIT(5)
#define PWR_KEY_LONG_IRQ	BIT(4)
#define PWR_KEY_SHORT_IRQ	BIT(3)
#define PWR_KEY_PRESS_IRQ	BIT(2)
#define PWR_WAKE0_DISCON_IRQ	BIT(1)
#define PWR_WAKE0_CON_IRQ	BIT(0)

#define PMC_LD_PEND_IRQ		BIT(0)

#define SYS_RESETN		BIT(10)
#define ALARM_INT		BIT(9)
#define GPADC_DEF		BIT(8)
#define KEY_SLONG_EN		BIT(7)

/* #define PWR_KEY		BIT(1) */
/* #define PWR_WAKE0		BIT(0) */

#define KEY_FILED	0xEE18
#define SLONG_POWER_DOWN_MODE	0
#define SLONG_REBOOT_MODE	1

#define COMMON_IRQ_SOURCRE	(PWR_KEY_RELEASE_IRQ | PWR_KEY_LONG_IRQ | \
				PWR_KEY_SHORT_IRQ | PWR_KEY_PRESS_IRQ | \
				PWR_WAKE0_CON_IRQ)

#define IRQ_SOURCRE	(COMMON_IRQ_SOURCRE | \
			ALARM_INT_IRQ | PWR_WAKE0_DISCON_IRQ)
			/* PWR_PE1_PUP | PWR_PE1_REN | PWR_PE0_PUP | \
			 * PWR_PE0_REN | SYS_RESETN_IRQ | GPADC_DET_IRQ
			 */
#define FB_EN_SOURCE	(ALARM_INT | KEY_SLONG_EN)
			/* PWR_KEY | PWR_WAKE0 | GPADC_DEF */

void csp_pmc_set_sys_stat(void __iomem *base);
u32 csp_pmc_get_con_stat(void __iomem *base);
void csp_pmc_unlock(void __iomem *base);
void csp_pmc_lock(void __iomem *base);
void csp_pmc_pe_disable(void __iomem *base);
void csp_pmc_ld_en(void __iomem *base, u32 en);
void csp_pmc_ld_int_en(void __iomem *base, u32 en);
void csp_pmc_ld_int_clr(void __iomem *base, u32 pending);
u32 csp_pmc_get_ld_pending(void __iomem *base);
u32 csp_pmc_get_clk_src_stat(void __iomem *base);
void csp_pmc_set_clk_src(void __iomem *base, u32 clk_src);
void csp_pmc_enable_irq_by_source(void __iomem *base, u32 enable);
void csp_pmc_disable_irq_by_source(void __iomem *base, u32 enable);
u32 csp_pmc_get_pm_sys_resetn_status(void __iomem *base);
void csp_pmc_pm_fb_en(void __iomem *base, u32 enable);
void csp_pmc_pm_fb_disabled(void __iomem *base, u32 enable);
void csp_pmc_set_irq_en(void __iomem *base, u32 value);
int csp_pmc_get_irq_en(void __iomem *base);
void csp_pmc_disable_irq_en(void __iomem *base);
u32 csp_pmc_get_irq_pending(void __iomem *base);
void csp_pmc_clear_irq_pending(void __iomem *base, u32 pending);
void csp_pmc_get_pwrkey_mask(u32 pending, u32 *pwrkey_mask);
void csp_pmc_set_pwrkey_slong_mode(void __iomem *base, u32 mode);
void csp_pmc_set_pd_mask_en(void __iomem *base, u32 en);
void csp_pmc_config_fanout_func(void __iomem *base, u32 mode);
void csp_pmc_set_fanout_output(void __iomem *base, u32 output, u32 value);
